Resistance to plate is a performance limiter for semiconductor structures, such as embedded dynamic random access memory (hereinafter “eDRAM”) access times. eDRAM is DRAM that is embedded on the same die as an ASIC or processor. DRAM is a type of semiconductor memory which stores information as data bits in capacitors on metal-oxide-semiconductor integrated circuits. Each bit is typically stored as an amount of electrical charge in a storage cell consisting of a capacitor and a transistor. Conventional semiconductor DRAM devices are formed in bulk substrate semiconductor material by implanting a well of either p-type or n-type material in a wafer of either type of material. Gates and source/drain diffusions are then manufactured using commonly known processes. Memory cells may be arrayed in a matrix manner.
Ion implantation is essential to modern integrated-circuit manufacturing. Conventional doping or modification of silicon and other semiconductor wafers relies on the technology, which may involve generating an ion beam and steering it into the substrate so that the ions come to rest beneath the surface of the substrate. Ions may be allowed to travel through a beam line at the energy at which they were extracted from a source material, or they can be accelerated or decelerated by direct current or radio-frequency electric fields. Conventional processes for implanted silicon create a high resistance connection (i.e. a connection that resists the flow of electricity therein) to the backside of capacitors, such as metal-on-metal capacitors, which can lead to elevated delays when such chips are operated at high frequency.